Distributed Virtual-time Scheduling in Rings (DVSR) is a dynamic bandwidth allocation algorithm for packet ring networks. This algorithm provides fair and/or guaranteed access rates for each node on the ring while maximizing spatial reuse and bandwidth usage. The DVSR algorithm attempts to achieve fairness based on the RIAS reference model of fairness for rings.
We are developing a 1 Gb/sec testbed implementation of DVSR on the Vitesse IQ2000 Network Processor. The ring's transit path has GigE interfaces and the station (ingress/egress) traffic has 8 100 Mb/sec ports.
We have completed development of a 100 Mb/sec emulation of an 8-node ring. Source code includes three files: the main assembly file, the memory initialization script, and the timer interrupt assembly file.
RIAS C code
Back to the Rice Packet Ring homepage